This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-336194, filed Nov. 2, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a manufacturing method of electronic devices such as semiconductor circuits (LSI) and magnetic circuits, and more particularly to an electronic device manufacturing method containing a step of filling a conductive film into the internal portion of a to-be-filled region such as an interconnection groove and contact/via hole by plating.
2. Description of the Related Art
Conventionally, an Al interconnection containing Al as a main component is often used for an interconnection of an LSI or the like. However, recently, an interconnection (Cu interconnection) containing copper (Cu) as a main component by the damascene method is dominantly used.
This is because Cu has characteristics of a lower resistivity than that of Al, and a higher melting point. As a result, a Cu interconnection using the damascene method has various advantages for miniaturization. More specifically, the RC delay is improved upon and the EM (electromigration) resistance is enhanced.
When a Cu interconnection is formed by use of the damascene method, it is necessary to form a Cu film on the entire surface so as to fill the Cu film into the internal portion of an interconnection groove, or an interconnection groove and contact hole previously formed in an interlayer dielectric.
As one of the forming methods of this type of Cu film, a method using electroplating is known. In this method, the inner wall of an interconnection groove or the like is previously coated with a Cu film (Cu seed film) used as a seed prior to formation of the Cu film. The Cu seed film is also called a xe2x80x9ccurrent introducing filmxe2x80x9d, and is formed by use of the sputtering method.
However, since the sputtering method does not provide good step coverage, the film thickness of a Cu seed film 63 becomes less in a portion near the bottom portion of an contact hole formed in an interlayer dielectric 61 as shown in FIG. 1 when the aspect ratio of the interconnection groove or contact hole increases, as the element is further miniaturized. On the other hand, in a portion near the opening portion of the interconnection groove or contact hole, an eaves-like overhang of the Cu seed film 63 is formed. In FIG. 1, reference numeral 62 denotes a barrier metal film, 64 denotes a Cu film used as an interconnection, and 65 denotes a Cu film of the underlying interconnection.
If the film thickness of the Cu seed film 63 is further reduced in the portion near the bottom portion of the contact hole, the function of the Cu seed film 63 used as the current introducing film is lost in this portion, and in the worst case, electroplating does not occur at all. That is, if the film thickness of the Cu seed film 63 is reduced in the portion near the bottom portion of the contact hole, the filling shape or buried shape of the Cu film 64 deteriorates.
The above problem can be solved by depositing a thick Cu seed film 63 by sputtering, but at this time, since the overhang becomes significantly large, a plating solution cannot be supplied to the bottom of the contact hole. Therefore, in this case, the filling shape of the Cu film 64 deteriorates.
As an attempt to solve the above problem, a method for forming a Cu thin film on a Cu seed layer by electroless plating after the relatively thin Cu seed layer having a small overhang is formed and before a Cu film is formed as an interconnection by electroplating is proposed.
However, the inventors of this application have found that the growth nucleus density of the Cu thin film formed on the Cu seed layer by electroless plating is low, and significantly uneven portions are formed on the surface of the Cu thin film. The uneven portions obstruct the electroplating and make it difficult to fill the Cu film into the contact hole or the like. As a result, the filling shape of the Cu film deteriorates.
As described above, there occurs a problem that it becomes difficult to form a Cu film having a good filling shape in the internal portion of the interconnection groove or contact hole by plating when the aspect ratio of the interconnection groove or contact hole increases as the element is further miniaturized. Therefore, it becomes necessary to provide an electronic device manufacturing method which can form a conductive film having a good filling shape in the internal portion of a to-be-filled region with high aspect ratio by plating.
An electronic device manufacturing method according to a first aspect of this invention comprises forming an insulating film above a substrate; forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film; forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region; forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film; and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
An electronic device manufacturing method according to a second aspect of this invention comprises forming an insulating film above a substrate; forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film; forming a first conductive film containing a preset material, so as to line an internal surface of the to-be-filled region; and forming a second conductive film on the first conductive film by plating, growth nucleus density of the second conductivity film being enhanced by use of the preset material.
An electronic device manufacturing method according to a third aspect of this invention comprises forming an insulating film above a substrate; forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film; forming a conductive amorphous film so as to line an internal surface of the to-be-filled region; and forming a conductive film on the conductive amorphous film by plating so as to fully fill the to-be-filled region via the conductive amorphous film.
An electronic device manufacturing method according to a fourth aspect of this invention comprises forming an insulating film above a substrate; forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film; forming a first copper film oriented mainly in a (111) direction so as to line an internal surface of the to-be-filled region; and forming a second copper film on the first copper film by plating so as to fill the to-be-filled region.